This invention relates in general to MOS capacitors and in particular, to MOS precision capacitors with low voltage coefficients and techniques for forming such MOS precision capacitors.
FIGS. 1-3 illustrate, as examples, three prior art MOS capacitor structures. In FIG. 1, a basic MOS capacitor 10 includes a p substrate 12 biased to a low reference voltage such as ground, an oxide layer 16 having a thickness "tox", a first electrode 14 isolated from the p substrate 12 by the oxide layer 16 formed over the p substrate 12, and a second electrode 15 connected to the p substrate 12 through a via 17. By applying a negative voltage to the first electrode 14, holes attracted towards the first electrode 14 form an accumulation layer 18 near the surface of the p substrate 12. The accumulation layer 18 thereupon acts as one plate of a parallel plate capacitor, the first electrode 14 acts as the other plate, and the oxide layer 16 acts as the dielectric medium.
In FIGS. 2 and 3, MOS capacitors 20 and 30 are respectively illustrated. Each of these capacitors has a lower voltage dependency than the MOS capacitor 10. In FIG. 2, the MOS capacitor 20 includes a p substrate 22 biased to a low reference voltage such as ground, a p region 23 formed in and having a higher dopant concentration than the p substrate 22, an oxide layer 26 formed over the p region 23 and the p substrate 22, a first electrode 24 formed above and isolated from the p region 23 by the oxide layer 26, and a second electrode 25 connected to the p substrate 22 through a via 27. In FIG. 3, a conventional n-mos transistor is connected as a capacitor to form the MOS capacitor 30. The MOS capacitor 30 includes a p substrate 32 biased to a low reference voltage such as ground, a threshold adjust region 39 formed in and having a higher dopant concentration than the p substrate 32, an oxide layer 36 formed over the p substrate 32, a first electrode 34 formed over the oxide layer 36 and the threshold adjust region 39, n+ regions 33 and 38 formed in the p substrate 32 and self aligned to the first electrode 34, and a second electrode 35 connected to the n+ region 33 through a via 37. The type of dopant used in forming the threshold adjust region 39 depends upon whether the n-mos transistor is an enhancement mode or depletion mode type. For an enhancement mode n-mos transistor, a p-type dopant is generally used, and for a depletion mode n-mos transistor, a n-type dopant is generally used in forming the threshold adjust region 39. In the MOS capacitors 20 and 30, the higher dopant concentrations (relative to the p substrate) in the p region 23 and the threshold adjust region 39 increase the minimum capacitances C.sub.min of their respective MOS capacitors, thereby reducing their voltage dependencies relative to that of the MOS capacitor 10; and in the MOS capacitor 30, n+ regions 33 and 38 reduce the signal frequency dependence of the MOS capacitor 30 relative to that of the MOS capacitor 10.
Typically, such MOS capacitors are formed in an integrated circuit including a plurality of p-mos and/or n-mos transistors. It is generally desirable in forming such an integrated circuit that the capacitances of its MOS capacitors track the capacitances of the plurality of p-mos and/or n-mos transistors. It is also generally desirable in forming such an integrated circuit that the voltages across its MOS capacitors be isolated from "ground bounce" or noise generated by the switching on and off of the plurality of p-mos and/or n-mos transistors. Prior art MOS capacitors are generally deficient in these respects. For additional details on prior art MOS capacitors and their characteristics, see, e.g., Weste, Neil H. E. et. al., Principles of CMOS VLSI Design, Addison-Wesley Publishing Company (1985), which details are herein incorporated by this reference.